Significant power is consumed in data buses operating at high frequency, particularly buses that use Series Stub Terminated Logic (SSTL) signaling and/or Thevenin terminations for impedance matching. When consumed power needs to be reduced, or when internal computer or particular device temperatures get too high, power consumption (and therefore heat generation) may be reduced by slowing data transfer by lowering the frequency of the clock signal applied to the phase-locked loops of the source and target devices.
However, because clock signals couple to the source and target devices by way of phase-locked loops, lowering the frequency of the clock signal causes the phase-locked loops to lose lock and thus forces them to re-lock, a process that may take several clock cycles. For this reason, power consumption and clock frequency are controlled at a macro scale, based on system temperature, device temperature, and/or overall data throughput of a plurality of bus transactions.